REV. 0

ADE7754

–39–

Interrupt Enable Register (0Fh)

When an interrupt event occurs in the ADE7754, the

IRQ logic output goes active low if the enable bit for this event is Logic 1 in this

register. The

IRQ logic output is reset to its default collector open state when the RSTATUS register is read. Table XVI describes the

function of each bit in the interrupt enable register.

Table XVI. IRQEN Register

Bit

Interrupt

Default

Location

Flag

Value

Description

0

AEHF

0

Enables an interrupt when there is a 0 to 1 transition of the MSB of the AENERGY register

(i.e., the AENERGY register is half-full).

1

SAGA

0

Enables an interrupt when there is a SAG on the line voltage of the Phase A.

2

SAGB

0

Enables an interrupt when there is a SAG on the line voltage of the Phase B.

3

SAGC

0

Enables an interrupt when there is a SAG on the line voltage of the Phase C.

4

ZXTOA

0

Enables an interrupt when there is a zero-crossing timeout detection on Phase A.

5

ZXTOB

0

Enables an interrupt when there is a zero-crossing timeout detection on Phase B.

6

ZXTOC

0

Enables an interrupt when there is a zero-crossing timeout detection on Phase C.

7

ZXA

0

Enables an interrupt when there is a rising zero crossing in voltage channel of the Phase A—

zero-crossing detection.

8

ZXB

0

Enables an interrupt when there is a rising zero crossing in voltage channel of the Phase B—

zero-crossing detection.

9

ZXC

0

Enables an interrupt when there is a rising zero crossing in voltage channel of the Phase C—

zero-crossing detection.

Ah

LENERGY

0

Enables an interrupt when the LAENERGY and LVAENERGY accumulations over LINCYC

are finished.

Bh

Reserved.

Ch

PKV

0

Enables an interrupt when the voltage input selected in the MMODE register is above the

value in the PKVLVL register.

Dh

PKI

0

Enables an interrupt when the current input selected in the MMODE register is above the

value in the PKILVL register.

Eh

WFSM

0

Enables an interrupt when a data is present in the waveform register.

Fh

VAEHF

0

Enables an interrupt when there is a 0 to 1 transition of the MSB of the VAENERGY register

(i.e., the VAENERGY register is half full).

0

0

0

0

0

0

0

0

F

E

D

C

B

A

9

8

INTERRUPT ENABLE REGISTER*

0

0

0

0

0

0

0

0

7

6

5

4

3

2

1

0

VAEHF

(APPARENT ENERGY REGISTER HALF FULL)

PKI

(CURRENT CHANNEL PEAK DETECTION)

PKV

(VOLTAGE CHANNEL PEAK DETECTION)

AEHF

(ACTIVE ENERGY REGISTER HALF FULL)

SAG

(SAG EVENT DETECT)

ZX

(ZERO-CROSSING TIMEOUT DETECTION)

ZX

(ZERO-CROSSING DETECTION)

LENERGY

(END OF THE LAENERGY AND LVAENERGY ACCUMULATION)

WFSM

(NEW WAVEFORM SAMPLE READY)

ADDR: 0Fh

*REGISTER CONTENTS SHOW POWER-ON DEFAULTS

RESERVED