17

Timing Diagrams

NOTE:

7. ALI and/or BLI may be high after t1, whereupon the ENABLE pin

may also be brought high.

FIGURE 38.

NOTE:

8. Between t1 and t2 the IN+ and IN- inputs must cause the OUT pin

to go through one complete cycle (transition order is not impor-

tant). If the ENABLE pin is low after the undervoltage circuit is

satisfied, the ENABLE pin will initiate the 10ms time delay during

which the IN+ and IN- pins must cycle at least once.

FIGURE 39.

DIS

ALI, BLI

8.5V TO 10.5V (ASSUMES 5% RESISTORS)

1.7V

12V, FINAL VALUE

DIS

LDEL

=10ms

t1

t2

8.3V TO 9.1V (ASSUMING 5% ZENER TOLERANCE)

12V, FINAL VALUE

5.1V

HIP4080