6

Input Audio Slot 2: Status Data

This slot delivers control register read data.

Input Audio Slot 3: PCM Record Left Channel

This slot contains an audio sample captured by the left chan-

nel ADC. The resolution of the ADC is 16 bits and is MSB

justified in the 20-bit slot.

Input Audio Slot 4: PCM Record Right Channel

This slot contains an audio sample captured by the right

channel ADC. The resolution of the ADC is 16 bits and is

MSB justified in the 20-bit slot.

Input Audio Slot 6: Microphone Record Channel

This slot contains an audio sample captured by the dedi-

cated microphone ADC. The resolution of the ADC is 16 bits

and is MSB justified in the 20-bit slot. This input allows

higher performance echo cancellation algorithms in speaker

phone applications.

Slots 5, 7-12: Reserved

Audio input slots 5, and 7-12 are reserved, and they are set

to “0”.

Low Power Modes

The HMP9701A may be put in a programmable powerdown

state to reduce power when no activity is required. The state of

powerdown is controlled by the Powerdown Register (26h).

This register provides 6 commands to powerdown various sec-

tions of the HMP9701A. A summary of the power down com-

mands is given in Table 10 with a more complete description

given in the Control Register Section. Note, the HMP9701A is a

fully static design which will preserve the contents of the inter-

nal control registers if the internal clock is stopped.

TABLE 6. BIT MAP FOR SLOT 1: STATUS DATA

BITS

DESCRIPTION

COMMENT

19:4

Control Register

Read Data

Stuffed with 0’s if slot tagged invalid

3:0

Reserved

Stuffed with 0’s

TABLE 7. BIT MAP FOR SLOT 3: LEFT CHANNEL RECORD DATA

BITS

DESCRIPTION

COMMENT

19:4

PCM Record Sample

Left Channel

16-Bit audio sample from Left

Record ADC

3:0

Reserved

Stuffed with 0’s

TABLE 8. BIT MAP FOR SLOT 4: RIGHT CHANNEL RECORD DATA

BITS

DESCRIPTION

COMMENT

19:4

PCM Record Sample

Right Channel

16-Bit audio sample from Right

Record ADC

3:0

Reserved

Stuffed with 0’s

FIGURE 6. AC LINK AUDIO INPUT FRAME

CODEC

READY

SLOT SLOT

SLOT

“0”

“0”

“0”

BIT 19

BIT 0 BIT 19

BIT 0

BIT 19

BIT 0

SYNC

SDATA_IN

BIT_CLK

12.288MHz

81.4ns

TAG PHASE

DATA PHASE

20.8

µs

(48kHz)

TIME SLOT “VALID” BITS

(“1” = TIME SLOT CONTAINS VALID DATA)

“1” = AC LINK INTERFACE

IS FUNCTIONAL

SLOT 1

SLOT 2

SLOT 12

12

2

1

TABLE 9. BIT MAP FOR SLOT 6: MICROPHONE RECORD DATA

BITS

DESCRIPTION

COMMENT

19:4

PCM Record Sample

Microphone Channel

16-Bit Audio Sample From

Dedicated Microphone ADC

3:0

Reserved

Stuffed with 0’s

TABLE 10. SUMMARY OF POWERDOWN REGISTER (26H)

BIT

FUNCTION

PR0

Input Mux and ADC Powerdown

PR1

DAC Powerdown

PR2

PR3

PR4

Digital Interface (AC-Link) Powerdown (External CLK Off)

PR5

Internal CLK Disable

HMP9701A