Data Sheet

DAC8412/DAC8413

Rev. G | Page 15 of 20

RESET

The RESET function can be used either at power-up or at any

time during DAC operation. The RESET function is independent

of CS. This pin is active low and sets the DAC output registers

to either center code for the DAC8412, or zero code for the

DAC8413. The reset-to-center code is most useful when the

DAC is configured for bipolar references and an output of 0 V

after reset is desired.

SUPPLIES

operating range is between 5 V and 15 V.

function. It is normally connected to +5 V. This pin is a logic

reference input only. It does not supply current to the device. If

does supply currents to the digital outputs when readback is used.

AMPLIFIERS

Unlike many voltage output DACs, the DAC8412 features buffered

voltage outputs. Each output is capable of both sourcing and

sinking 5 mA at ±10 V, eliminating the need for external

amplifiers when driving 500 pF or smaller capacitive load in

most applications. These amplifiers are short-circuit protected.

Table 6. DAC8412/DAC8413 Logic Table

A1

A0

R/W

CS

RS

LDAC

Input Register

Output Register

Mode

DAC

L

L

L

L

H

L

Write

Write

Transparent

A

L

H

L

L

H

L

Write

Write

Transparent

B

H

L

L

L

H

L

Write

Write

Transparent

C

H

H

L

L

H

L

Write

Write

Transparent

D

L

L

L

L

H

H

Write

Hold

Write input

A

L

H

L

L

H

H

Write

Hold

Write input

B

H

L

L

L

H

H

Write

Hold

Write input

C

H

H

L

L

H

H

Write

Hold

Write input

D

L

L

H

L

H

H

Read

Hold

Read input

A

L

H

H

L

H

H

Read

Hold

Read input

B

H

L

H

L

H

H

Read

Hold

Read input

C

H

H

H

L

H

H

Read

Hold

Read input

D

X

X

X

H

H

L

Hold

Update all output registers

All

X

X

X

H

H

H

Hold

Hold

Hold

All

X

X

X

X

L

X

All registers reset to midscale/zero-scale1

All

X

X

X

H

X

All registers latched to midscale/zero-scale1

All

1

DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = logic low; H = logic high; X = don’t care. Input and output registers are transparent when asserted.