ACE25C160G

Uniform SECTOR Dual and Quad Serial Flash

VER 1.5

16

Dual I/O Fast Read (BBH)

The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the

capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock by

SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are

shifted out 2-bit per clock cycle from SI and SO. The command sequence is shown in followed

Figure10. The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out.

Dual I/O Fast Read With “Continuous Read Mode”

The Dual I/O Fast Read command can further reduce command overhead through setting the

“Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous

Read Mode” bits (M7-0) =AXH, then the next Dual I/O Fast Read command (after CS# is raised and

then lowered) does not require the BBH command code. The command sequence is shown in

followed Figure11. If the “Continuous Read Mode” bits (M7-0) are any value other than AXH, the next

command requires the first BBH command code, thus returning to normal operation. A “Continuous

Read Mode” Reset command can be used to reset (M7-0) before issuing normal command.

Figure10. Dual I/O Fast Read Sequence Diagram (M7-0= 0XH or not AXH)