ACE25C320G

Uniform SECTOR Dual and Quad Serial Flash

VER 1.5

15

Figure8. Dual Output Fast Read

Sequence Diagram

Quad Output Fast Read (6BH)

The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte,

each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out

4-bit per clock cycle from IO3, IO2, IO1 and IO0. The command sequence is shown in followed

Figure9. The first byte addressed can be at any location. The address is automatically incremented to

the next higher address after each byte of data is shifted out.

Figure9. Quad Output Fast Read Sequence Diagram