ACE25C400G

Uniform SECTOR Dual and Quad Serial Flash

VER 1.5

29

Read Security Registers (48H)

The Read Security Registers command is similar to Fast Read command. The command is followed

by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of

SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a

Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location.

The address is automatically incremented to the next higher address after each byte of data is shifted

out. Once the A9-A0 address reaches the last byte of the register (Byte 3FFH), it will reset to 000H,

the command is completed by driving CS# high.

Address

A23-A16

A15-A8

A7-A0

Security Registers 1

00H

01H

Byte Address

Security Registers 2

00H

02H

Byte Address

Security Registers 3

00H

03H

Byte Address

Figure27. Read Security Registers command Sequence Diagram

Write Enable for Volatile Status Register (50h)

The non-volatile Status Register bits described on page 40 can also be written to as volatile bits.

During power up reset, the non-volatile Status Register bits are copied to a volatile version of the

Status Register that is used during device operation. This gives more flexibility to change the system

configuration and memory protection schemes quickly without waiting for the typical non-volatile bit

write cycles or affecting the endurance of the Status Register non-volatile bits. To write the volatile

version of the Status Register bits, the Write Enable for Volatile Status Register (50h) command

must be issued prior to each Write Status Registers (01h) command. Write Enable for Volatile Status

Register command (Figure 29) will not set the Write Enable Latch (WEL) bit, it is only valid for the

next following Write Status Registers command, to change the volatile Status Register bit values.