Data Sheet S13368EJ3V0DS00

13

µµµµ PD16682

(1) 80 Series Parallel Interface

When 80 series parallel data transfer has been selected, data is written to the

µ PD16682 at the rising edge of the

/WR signal. The data is output to the data bus when the /RD signal is L.

Figure 5

/CS1

(CS2=H)

/WR

/RD

DBn

Hi-Z

Hi-Z

Data write

Data read

Valid data

(2) 68 Series Parallel Interface

When 68 series parallel data transfer has been selected, data is written at the falling edge of the E signal when the

R,/W signal is L. During the data read operation, the data bus enters the output status when the R,/W signal is H,

outputs valid data at the rising edge of the E signal, and enters the high-impedance state at the falling edge of the

R,/W signal (R,/W = L)

Figure 5

/CS1

(CS2=H)

R,/W

E

DBn

Hi-Z

Hi-Z

Hi-Z

Invalid data

Valid data