DocID024408 Rev 2

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ECC error hardware exceptions

3

ECC error hardware exceptions

There are two types of ECC fault notifications that are generated by hardware of SPC650x

microcontroller.

•

ECSM module interrupts

•

Exceptions events of the core

3.1

ECSM module interrupts

ECSM module interrupt can be generated in the case of both kinds of ECC faults, 1-bit and

2-bit, and they are further distinguished for RAM and Flash memory. This interrupt belongs

among external peripheral interrupts that are linked to IVOR4 vector. Figure 2 shows block

scheme of ECSM interrupt routing in the microcontroller.

All interrupts that can be generated by ECSM module are configurable and can be masked

by the user in ECR register.

Figure 2. ECSM interrupt generation

3.2

Core exceptions

In all cases, non-correctable ECC errors that occur during instruction fetch or data read

cause generation of core exceptions because of bus transaction errors between Z0 core

and given memory target. Core exception events cannot be masked and should be handled

properly to solve the issue.

Several exceptions can be generated based on type of memory access, instruction fetch or

data fetch, and configuration of machine state register MSR, see Table 5.

Single bit interrupts does not generate core exceptions, they can be caught by enabled

ECSM interrupts. Not all non-correctable ECC errors are signaled by core exceptions like

ECC error during discarded not taken branch fetch, but they are signaled by ECSM module.

ECC config reg

ECC status reg

&

ECC catch

registers

INTC

module

IVOR4 vector

External interrupt

to Z0 core

Z0 core

ECSM module

1-bit ECC fault

Non-correctable

ECC fault

1-bit ECC fault

Non-correctable

ECC fault

RAM

memory

CFlash

/ Dflash

memory

Interrupt

Handler