Configuration of the CAN bit timing

AN2352

12/20

1.6

Calculation of the bit timing parameters

Usually, the calculation of the bit timing configuration starts with a desired bit rate or bit time.

The resulting bit time (1/bit rate) must be an integer multiple of the system clock period.

to the desired bit time, allowing iterations of the following steps.

The first part of the bit time to be defined is the Prop_Seg. Its length depends on the delay

times measured in the system. A maximum bus length as well as a maximum node delay

must be defined for expandable CAN bus systems. The resulting time for Prop_Seg is

same length, Phase_Seg2

= Phase_Seg1, otherwise Phase_Seg2 = Phase_Seg1 + 1.

The minimum nominal length of Phase_Seg2 must also be considered. Phase_Seg2 may

not be shorter than the CAN controller’s information processing time, which, depending on

The length of the synchronization jump width is set to its maximum value, which is the

minimum of 4 and Phase_Seg1.

The oscillator tolerance range necessary for the resulting configuration is calculated by the

formulas expressed in

Section 1.4: System clock tolerance range.

If more than one configuration is possible, that configuration allowing the highest oscillator

tolerance range should be chosen.

CAN nodes with different system clocks require different configurations to attain the same

bit rate. The calculation of the propagation time in the CAN network, based on the nodes

with the longest delay times, is done once for the whole network.

The CAN system’s oscillator tolerance range is limited by that node with the lowest tolerance

range.

The calculation may show that bus length or bit rate must be decreased or that the oscillator

frequencies’ stability must be increased in order to find a protocol compliant configuration of

the CAN bit timing.

The resulting configuration is written into the bit timing register:

(Phase_Seg2 - 1) and (Phase_Seg1 + Prop_Seg - 1) and (SynchronizationJumpWidth - 1)

and (Prescaler - 1)