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AN458 APPLICATION NOTE

When the voltage on pin 12 exceeds 5V, the transistor Q1 switches off and the delay capacitor (Cd) starts to

charge through an internal current generator of about 110

µA. When the voltage on pin 9 reaches 4.5V, the out-

put of the comparator (B) switches low and pin 10 goes high.

As the output is an open collector transistor (Q2), a pull-up external resistor is required.

On the contrary, when the Reset input voltage goes below 5V, with an hysteresis of 100mV, the comparator (A)

triggers again and sets istantaneously the voltage on pin 10 low, therefore forcing to saturation the Q1 transistor,

that starts the fast discharge of the delay capacitor.

As shown in the block diagram, the Reset output is low when the UVLO or The INHIBIT signals are present.

Inside the chip there is a digital filter that prevents the Reset circuit activation if Vout drops below the reset

threshold for less than 2s.

In this way the Reset circuit neglects very fast drops in the output voltage. In fig.15 and Fig.16 are shown re-

spectively the Reset circuit Waveforms and a typical application.

Figure 13. Current Limiter

Figure 14.