AN1762 datasheet(5/53 Pages) STMICROELECTRONICS

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AN1762 APPLICATION NOTE

Figure 4. High side gate drivers supply voltage versus supply voltage.

Note that VS must be connected to both VSA and VSB since the bootstrap voltage (at VBOOT pin) is the same for

the two H-bridges. The integrated DMOS have a rated Drain-Source breakdown voltage of 60V. However VS

should be kept below 52V, since in normal working conditions the DMOS see a Vds voltage that will exceed VS

supply. In particular, during a phase change (when each output of the same H-bridge switches from VS to GND

or vice versa, for example to reverse the current in the load) at the beginning of the dead-time (when all the

DMOS are off) the

SENSE pin sees a negative spike due to a not negligible parasitic inductance of the PCB

path from the pin to GND. This spike is followed by a stable negative voltage due to the drop on RSENSE. One

of the two

OUT pins of the bridge sees a similar behavior, but with a slightly larger voltage due to the forward

recovery time of the integrated freewheeling diode and the forward voltage drop across it (see Figure 5). Typical

duration of this spike is 30ns. At the same time, the other

OUT pin of the same bridge sees a voltage above VS,

due to the PCB inductance and voltage drop across the high-side (integrated) freewheeling diode, as the current

reverses direction and flows into the bulk capacitor. It turns out that the highest differential voltage can be ob-

served between the two

OUT pins of the same bridge, during the dead-time at a phase change, and this must

always be kept below 60V [3].

Figure 5. Currents and voltages during the

dead time at a phase change.

VS [V]

VBOOT - VS

[V]

6.4

6.8

7.2

7.6

8 .5

9 .5

10.5

SENSE

OUT

SENSE*I

SENSE*I+VF(Diode)

PCB Parasitic

Inductance

PCB Parasitic

Inductance

Bulk Capacitor

Equivalent Circuit

ESR

ESL

SENSE

S+VF(Diode)

Dangerous

High Differential Voltage

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