AN2783 datasheet(11/47 Pages) STMICROELECTRONICS

11 / 47 page

AN2783

Board layout

11/47

Figure 7.

Bottom layer

4.1

Input/output connectors

In Figure 3 the main input / output connections of the reference board are presented:

●

J1 is the RJ45 connector for the PoE input, with data and power applied through the

CAT5 cable (as an alternative, a positive voltage between 30 V and 60 V can be applied

to test points TP1 + and TP2 -)

●

J2 is the RJ45 data output

●

J3 is the power jack for AUXI input (as an alternative, the test points TP 3 + and TP4 -

can be used)

●

J4 is the power jack for AUXII input (as an alternative, the test points TP5 + and TP9 -

can be used)

●

J5 is the DC output connector

4.2

Notes

●

Please note that the use of TP1 and TP2 limits the voltage polarity applied and that

these points are after the data transformer and diode bridges.

●

AUXII is not protected against reverse polarity applied to it.

●

For synchronization tests the capacitor C40 =100 pF must be mounted. Please take

care when using test point TP13 because this is a high impedance point that can easily

pick up noise from the board.

●

Resistive or electronic loads can be used as loads. Limit the output capacitance

externally applied in order to not impact the loop compensation.

●

As an input source a DC power supply with 60 V and 2 A capability is required.

●

For auxiliary inputs a DC source of 60 V and 3 A capability is recommended.

AN2783 데이터시트(PDF) 11 Page - STMicroelectronics