AN2839 datasheet(13/40 Pages) STMICROELECTRONICS

13 / 40 page

AN2839

Designing an application with L6228

Doc ID 15104 Rev 1

13/40

1.9

Input logic pins

CW/CCW, CONTROL, RESET, HALF/FULL, CLOCK are CMOS/TTL-compatible logic input

pins. The input comparator has been realized with hysteresis to ensure the required noise

immunity is met. Typical values for turn-on and turn-off thresholds are Vth,ON = 1.8 V and

Vth,OFF = 1.3 V. As shown in Figure 10, these pins are ESD-protected (2 kV human-body

electro-static discharge), and can be directly connected to the logic outputs of a µC; a series

resistor is generally not recommended as it could cause inducted noise and disturb the

inputs. All logic pins enforce a specific behavior and cannot be left unconnected.

Figure 10.

Logic input pins

1.10

EN pin

The EN pin is bi-directional: as an input, with a comparator similar to the other logic input

pins (TTL/CMOS with hysteresis), it controls the state of the Power DMOS. When this pin is

at a low logic level, all the Power DMOS’s are turned off. The EN pin is also connected to the

open-drain output of the protection circuit that will pull the pin to GND if overcurrent or over-

temperature conditions exist. For this reason, the EN pin must be driven through a series

resistor of 2.2 kW minimum (for 5 V logic), to allow the voltage at the pin to be pulled below

the turn-off threshold.

A capacitor (C1 in Figure 5 on page 8) connected between the EN pin and GND is also

recommended to reduce the RMS value of the output current when overcurrent conditions

persist (see Section 1.12). The EN pin must not be left unconnected.

Figure 11.

EN input pin

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