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AN3027 데이터시트(PDF) 23 Page - STMicroelectronics

부품명 AN3027
상세설명  How to design a transition-mode PFC pre-regulator
PDF  41 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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AN3027 데이터시트(HTML) 23 Page - STMicroelectronics

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AN3027
Designing a TM PFC
Doc ID 16134 Rev 4
23/41
within the range 0 to 3 V of VMULT and the range 0 to 1.16 V (typ.) of VCS, while the minimum
guaranteed value of the maximum slope of the characteristics family (typ.) is:
Equation 48
The voltage on the MULT pin is also used to derive the information from the RMS mains
voltage for the VFF compensation.
We suggest the following procedure to properly set the operating point of the multiplier. First,
the maximum peak value for VMULT, VMULTmax is selected. This value, which occurs at
maximum mains voltage, should be 3 V or nearly so in wide-range mains and less in case of
single mains. The sense resistor selected is Rs = 0.27 Ω as given in Equation 44. According
to the L6563S datasheet and to the linearity setting of the pin, the maximum voltage
accepted on the multiplier input is:
where ILpk and Rs have been already calculated, 1.66 is the multiplier maximum slope given
in the datasheet.
From
(15) the maximum required divider ratio is calculated as:
Equation 49
Supposing a 60 µA current flowing into the multiplier divider, the lower resistor value can be
calculated:
Equation 50
A commercial resistor of 51 k
Ω for the lower resistor is selected. The upper resistor value
can now be calculated as:
Equation 51
In this application example RmultH = 6.6 MΩ and RmultL = 51 kΩ have been selected. Please
note that for RmultH a resistor with a suitable voltage rating (>400 V) is needed, or more
resistors in series must be used.
The voltage on the multiplier pin with the selected component values is re-calculated at
minimum line voltage (0.93 V) and at maximum line voltage (2.74 V). So the multiplier works
correctly within its linear region.
Pin 5 (voltage feed-forward): The power stage gain of PFC pre-regulators varies with the
square of the RMS input voltage as well as the crossover frequency fc of the overall open-
loop gain because the gain has a single pole characteristic. This leads to large trade-offs in
(15)
V
V
66
.
1
dV
dV
MULT
CS
=
V
3
VMULTmax =
3
max
max
MULT
p
10
8
Vac
265
2
V
00
.
3
VAC
2
V
k
−
⋅
=
⋅
=
⋅
=
Ω
=
µ
=
µ
=
k
50
A
60
V
00
.
3
A
60
V
R
max
MULT
multL
Ω
=
Ω
⋅
⋅
−
=
−
=
−
−
M
319
.
6
k
51
10
8
10
8
1
R
k
k
1
R
3
3
multL
p
p
multH



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