Test results and significant waveforms

AN4077

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Doc ID 022997 Rev 1

auxiliary winding with the charge pump circuit takes over. At the same time, the output

voltage rises from peak value of the rectified mains to the nominal value of the PFC output

voltage. The good margin phase of the compensation network allows a clean startup,

without any large overshoot.

4.4

PFC_OK pin and feedback failure (open loop) protection

During normal operation, the voltage control loop provides for the output voltage (Vout) of

the PFC pre-regulator close to its nominal value, set by the resistors ratio of the feedback

output divider. In the L6564H a pin of the device (PFC_OK, pin #6) has been dedicated to

monitoring the output voltage with a separate resistor divider made up of R3, R6, R11 (high)

and R15 (low), see

Figure 2. This divider is selected so that the voltage at the pin reaches

2.5 V if the output voltage exceeds a preset value (Vovp), usually larger than the maximum

Vout that can be expected, also including worst-case load/line transients.

For the EVL6564H-100W we have:

–

Vo = 400 V

–

Vovp = 434 V

Select:

–

R3+R6+R11= 8.8 M

Ω

then:

–

R15 = 8.8 M

Ω ·2.5/(434-2.5) = 51 kΩ

Once this function is triggered, the gate drive activity is immediately stopped until the

voltage on the PFC_OK pin drops below 2.4 V. An example is reported in

Figure 29.

Note that both feedback dividers connected to the L6564H pin #1 (INV) and pin #6

(PFC_OK) can be selected without any constraints. The unique criterion is that both dividers

Figure 27.

60 Hz-full load

Figure 28.

50 Hz-full load