| 전자부품 데이터시트 검색엔진 |
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UPD3728 데이터시트(PDF) 13 Page - NEC |
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UPD3728 데이터시트(HTML) 13 Page - NEC |
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13 / 24 page ![]() µPD3728 13 DATA SHEET S13878EJ1V0DS00 TIMING CHART 6 (Line clamp mode, for each color) Symbol MIN. TYP. MAX. Unit t12 3000 10000 ns t13, t14 0 50 ns t15, t16 900 1000 ns t17, t18 100 1000 ns t19 200 t12 ns t20, t21 0 20 ns Note Set the φRB to high level during this period. Remark Inverse pulse of the φTG1 to φTG3 can be used as φCLB. φ1 (φ10), φ2 (φ20) cross points φ1L, φ2 (φ20) cross points Remark Adjust cross points ( φ1 (φ10), φ2 (φ20)) and (φ1L, φ2 (φ20)) with input resistance of each pin. 2 ( 20) 1 ( 10) 2 ( 20) 2 V or more 2 V or more φ φφ φ φ φ φ 1L 2 V or more 0.5 V or more TG1 to TG3 1 ( 10) 2 ( 20) 1L RB CLB t12 Note t14 t13 90 % 10 % 90 % 10 % t15 t20 t21 t18 t17 90 % 90 % t19 t16 φ φ φ φ φ φ φ φ φ |
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