DocID025366 Rev 2

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AN4374

PCB layout guidelines

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vias could be a good solution.The best implementation is represented by copper

filled vias.

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On each inner layer, a copper area must be provided for dissipation (if possible, at

least 4 times wider than the package dimensions). A good condition is to have at

least a power layer as an entire copper area (e.g. GND layer).

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Traces for pin connection must be enlarged till layout constrains allow.

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Several devices in power dissipation on the same board must be adequately

spaced.