AN4662 datasheet(39/43 Pages) STMICROELECTRONICS

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AN4662

First-in first-out (FIFO) buffer

Figure 17: Stream mode

Stream mode is intended to be used for reading all 32 samples of FIFO within an ODR

after receiving an Overrun signal. However, also a watermark interrupt CTRL3 (INT1_FTH),

CTRL6 (INT2_FTH) can be enabled in order to read data from the FIFO and leave free

memory slots for incoming data.

8.4.4

Stream-to-FIFO mode

In Stream-to-FIFO mode (FIFO_CTRL(FMODE2:0) = 011), FIFO behavior changes

according to the IG_SRC1 (IA) bit. When the IG_SRC1(IA) bit is equal to '1', FIFO operates

in FIFO mode, when the IG_SRC1 (IA) bit is equal to '0', FIFO operates in Stream mode.

Interrupt generator 1 has to be properly set through the IG_CFG1, IGTHS_X1, IGTHS_Y1

and IGTHS_Z1 registers.

The CTRL7 (LIR1) bit should be set to '1' in order to latch the interrupt status and preserve

the FIFO content. If the interrupt is not latched and the interrupt condition disappears, the

FIFO behavior switches to Stream mode, overwriting the FIFO content.

8.4.5

Bypass-to-Stream mode

In Bypass-to-Stream mode (FIFO_CTRL (FMODE [2:0]) = 100) the FIFO buffer is reset

(By-pass mode) when G_SRC1 (IA) is equal to '0', it starts to collect data and to operate in

Stream mode when G_SRC1 (IA) is equal to '1'.

Interrupt generator 1 has to be properly set through the IG_CFG1, IGTHS_X1, IGTHS_Y1

and IGTHS_Z1 registers.

The CTRL7 (LIR1) bit should be set to '1' in order to latch the interrupt status and preserve

the FIFO content. If the interrupt is not latched and interrupt condition disappears, the FIFO

behavior switches to Bypass and the content is reset.

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