전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

LT4321 데이터시트(PDF) 7 Page - Linear Technology

부품명 LT4321
상세설명  PoE Ideal Diode Bridge Controller
PDF  12 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  LINER [Linear Technology]
홈페이지  http://www.linear.com
Logo LINER - Linear Technology

LT4321 데이터시트(HTML) 7 Page - Linear Technology

Back Button LT4321 Datasheet HTML 3Page - Linear Technology LT4321 Datasheet HTML 4Page - Linear Technology LT4321 Datasheet HTML 5Page - Linear Technology LT4321 Datasheet HTML 6Page - Linear Technology LT4321 Datasheet HTML 7Page - Linear Technology LT4321 Datasheet HTML 8Page - Linear Technology LT4321 Datasheet HTML 9Page - Linear Technology LT4321 Datasheet HTML 10Page - Linear Technology LT4321 Datasheet HTML 11Page - Linear Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 12 page
background image
LT4321
7
4321f
For more information www.linear.com/LT4321
applicaTions inForMaTion
Shutting down the LT4321 does not disconnect the load.
The external MOSFETs are shorted gate to source and
bridge current is carried by the MOSFETs’ body diodes.
The eight body diodes will act like two traditional diode
bridges.
At light load, the power dissipated in the forward drop of
the body diodes will be less than the power dissipated by
the LT4321 quiescent current. In applications with a low
power sleep mode, the LT4321 can optionally be shut
down to save power if the load current is less than 20mA.
EXTERNAL INTERFACE AND COMPONENT SELECTION
Bypass Capacitance
A 0.1μF ceramic capacitor must be placed across the
OUTP and OUTN pins.
In PD applications, the IEEE 802.3 standard limits the
port capacitance at the PD interface (CPD) to 0.12μF. The
LT4321 and the PD interface controller both need local
bypass capacitance, but they can share the same 0.1μF
capacitor. If the LT4321 and the PD interface controller
cannot both be positioned next to a shared bypass capaci-
tor, split the CPD capacitance between the two chips by
placinga0.047μFceramicclosetotheLT4321andanother
0.047μF ceramic close to the PD interface controller.
A 10μF or greater capacitance must be connected across
OUTP and OUTN pins when the LT4321 is enabled. In
PoE applications it is sufficient for the CPORT capacitor to
be connected by the PD interface controller’s hot swap
FET. In non PoE applications the CPORT capacitor may be
permanently connected between OUTP and OUTN.
Figure 2. Leakage Current at 125°C
Table 1. Conditions for Ideal Bridge Mode on IN12/IN36
PoE MODE
OUTP
EN | EN
IN12
IN36
IN45
IN78
TG12
TG36
BG12
BG36
Detect/Class
< VUVLO
X
X
X
X
X
OFF
Class/Inrush
> VUVLO
O
Power ON
1
> OUTP
< OUTN
X
X
ON
OFF
OFF
ON
< OUTN
> OUTP
OFF
ON
ON
OFF
|IN12 – IN36| <
OUTP – OUTN
> OUTN
OFF
< OUTP
Table 2. Conditions for Ideal Bridge Mode on IN45/IN78
PoE MODE
OUTP
EN | EN
IN12
IN36
IN45
IN78
TG45
TG78
BG45
BG78
Detect/Class
< VUVLO
X
X
X
X
X
OFF
Class/Inrush
> VUVLO
O
Power ON
1
X
X
> OUTP
< OUTN
ON
OFF
OFF
ON
< OUTN
> OUTP
OFF
ON
ON
OFF
|IN45 – IN78| <
OUTP – OUTN
> OUTN
OFF
< OUTP
VIN (V)
0
0
150
200
300
15
4321 F02
100
50
250
5
10
20
25
LT4321 SHUTDOWN MODE
B2100 SCHOTTKY BRIDGE



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com