LTC2053/LTC2053-SYNC



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Input Current

in an input charging current during each input sampling

the input current would go to zero for DC inputs.

In reality, there are additional parasitic capacitors which

voltage. For example, the parasitic bottom plate capacitor

to the voltage on the –IN pin every cycle. The resulting

input charging current decays exponentially during each

If the voltage disturbance due to these currents settles

before the end of the sampling period, there will be no

errors due to source resistance or the source resistance

no DC errors occur due to this input current.

In the Typical Performance Characteristics section of this

data sheet, there are curves showing the additional error

from non-zero source resistance in the inputs. If there

are no large capacitors across the inputs, the amplifier is

less sensitive to source resistance and source resistance

mismatch. When large capacitors are placed across the

inputs, the input charging currents previously described

result in larger DC errors, especially with source resistor

mismatches.

Power Supply Bypassing

TheLTC2053usesasampleddatatechniqueand,therefore,

contains some clocked digital circuitry. It is, therefore,

sensitive to supply bypassing. For single or dual supply

operation, a 0.1µF ceramic capacitor must be connected

possible.

Synchronizing to an External Clock

(LTC2053-SYNC Only)

TheLTC2053hasaninternallygeneratedsampleclockthat

is typically 3kHz. There is no need to provide the LTC2053

with a clock. However, in some applications, it may be

desirable for the user to control the sampling frequency

more precisely to avoid undesirable aliasing. This can be

done with the LTC2053-SYNC. This device uses Pin 1 as a

clock input whereas the LTC2053 uses Pin 1 as an enable

pin. If CLK (Pin 1) is left floating on the LTC2053-SYNC,

the device will run on its internal oscillator, similar to the

LTC2053. However, if not externally synchronizing to a

system clock, it is recommended that the LTC2053 be

used instead of the LTC2053-SYNC because the LTC2053-

SYNC is sensitive to parasitic capacitance on the CLK pin

when left floating. Clocking the LTC2053-SYNC is accom-

plished by driving the CLK pin at 8 times the desired

sample clock frequency. This completely disables the

internal clock. For example, to achieve the nominal

LTC2053sampleclockrateof3kHz,a24kHzexternalclock

should be applied to the CLK pin of the LTC2053-SYNC.

applicaTions inForMaTion

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2053 F01

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Figure 1