5 - Debug management

AN2156

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5

Debug management

5.1

JTAG debug port pins

The JTAG interface is a special synchronous serial port and provides access to the internal

scanchains and the debug logic. Some of these scanchains are around the ARM core and the

Embedded ICE Unit. With these it is possible to insert data into and read from the processor’s

pipeline, to program breakpoints and watchpoints and to control the debugging.

Since the JTAG port is an integral part of the ARM core it is available on every device and thus

also allows in-system debugging and in-system flash-programming directly in the target

application. The JTAG interface pins consist of the following signals:

Table 3.

JTAG interface signals

Std name

STR73x name

Direction/Description

Function

nTRST

JTRST

Test Reset (from JTAG

equipment)

This active LOW open-collector is used to

reset the JTAG port and the associated

debug circuitry. It is asserted at power-up by

each module, and can be driven by the JTAG

equipment.

TDI

JTDI

Test data in (from JTAG

equipment)

TDI goes down the stack of modules to the

motherboard and then back up the stack,

labelled TDO, connecting to each

component in the scan chain.

TMS

JTMS

Test mode select (from

JTAG equipment)

TMS controls transitions in the tap controller

state machine. TMS connects to all JTAG

components in the scan chain as the signal

flows down the module stack.

TCK

JTCK

Test clock (from JTAG

equipment)

TCK synchronizes all JTAG transactions.

TCK connects to all JTAG components in the

scan chain. Series termination resistors are

used to reduce reflections and maintain

good signal integrity. TCK flows down the

stack of modules and connects to each

JTAG component. However, if there is a

device in the scan chain that synchronizes

TCK to some other clock, then all down-

stream devices are connected to the RTCK

signal on that component.

RTCK

GND

(not used)

Return TCK (to JTAG

equipment)

Some devices sample TCK (for example a

synthesizable core with only one clock), and

this has the effect of delaying the time that a

component actually captures data. Using a

mechanism called adaptive clocking, the

RTCK signal is returned by the core to the

JTAG equipment, and the clock is not

advanced until the core had captured the

data. In adaptive clocking mode, the

debugging equipment waits for an edge on

RTCK before changing TCK.