AN2549

Modified features

14/33

running in Power Down mode and the on-chip main oscillator clock is used as the

reference.

●

When the PLL is used, the CPU frequency range is 16 to 64 MHz.

Figure 1: ST10F272Z2 clock generation diagram gives a simplified description of the CPU

clock generation. Depending on the multiplication factor selected via Port0 at reset, values

are set for each stage. The CPU clock is in fact generated mainly from a VCO with the

following characteristics:

●

input range: 1 to 3.5 MHz, which explains the Prescaler that divides the XTAL

frequency

●

output range: 64 to 128 MHz that is then divided through Divider1 to generate the CPU

clock

Figure 1.

ST10F272Z2 clock generation diagram

Table 11: ST10F269Zx vs ST10F272Z2 PLL ratio lists the new PLL multiplication factors

and the corresponding frequency ranges for the ST10F272Z2.

Table 11.

ST10F269Zx vs ST10F272Z2 PLL ratio

P0.15-13

(P0H.7-5)

PLL multiplication factor

ST10F272Z2 main oscillator

ST10F269Zx

ST10F272Z2

Input range

(MHz)

CPU clock range

(MHz)

1

1

1

x 4

x 4

4 to 8

16 to 32

1

1

0

x 3

x 3

5.34 to 8

16.02 to 24

1

0

1

x 2

x 8

4 to 8

32 to 64

1

0

0

x 5

x 5

6.4 to 8

32 to 40

0

1

1

x 1

x 1

1 to 64

1 to 64

0

1

0

x 1.5

x 10

4 to 6.4

40 to 64

0

0

1

x 0.5

x 0.5

4 to 8

2 to 4

0

0

0

x 2.5

x 16

4

64

Prescaler

VCO

Divider1

Divider2

Phase Comparator