Interfacing with an 8-bit NAND Flash memory

AN2784

22/31

Doc ID 14779 Rev 4

Figure 10.

NAND memory access timing

4.1.1

Typical use of the FSMC to interface with a NAND memory

The STM32F10xxx FSMC NAND Flash controller can configure Bank2 or Bank3 to support

NAND Flash memories.

The banks are selected using the Chip Select signals, as each bank is associated with a

specific Chip Select.

To enable communication with the NAND Flash devices, the FSMC NAND Flash controller

has to be initialized to meet the characteristics of the NAND Flash devices: features, timings,

data width, etc.

In this application note, the Numonyx NAND512W3A is used as the reference. This memory

has the same access protocol as many other NAND Flash memories on today’s market.

NAND512W3A characteristics:

●

NAND interface: x8 bus width, multiplexed address/ data

●

Page size: x8 device: (512 + 16 spare) bytes

●

Page Read/Program timings:

–

Random access: 12 µs (3 V)/15 µs (1.8 V) (max)

–

Sequential access: 30 ns (3 V)/50 ns (1.8 V) (min)

–

Page Program time: 200 µs (typ)

NCE

NOE

NWE

Write

Data

Read

Data

SET + 1

WAIT + 1

HOLD + 1

HCLK

A[25:0]

HiZ + 1

ai15183