AN2834 datasheet(41/45 Pages) STMICROELECTRONICS

41 / 45 page

DocID15067 Rev 2

41/45

AN2834

How to get the best ADC accuracy

3.4.4

Source of described problem - ADC design

The following sections list some possible causes for the charging of the internal sampling

capacitor Csh. This is not an exhaustive list; only the main possible sources of the ADC

design are listed.

Parasitic switch capacitance effect

The sampling switch inside ADC sampling circuit (see Figure 33) is not ideal. In reality the

sample and hold switch (S1) is designed as 2 transistors (PMOS and NMOS, see

Figure 37):

Figure 37. Implementation of sampling switch

The switch is controlled by the gate voltages of transistors (inverted signal on PMOS

transistor). This design is a standard bidirectional switch (for rail to rail range of input Uin

voltages). Both transistors have parasitic capacitances between gate and source.

If those capacitances are charged (close to the switch), then their charge can be transferred

to the sampling capacitor (see Figure 38).

Figure 38. Parasitic capacitances of sampling switch

This charging and discharging currents (PMOS and NMOS asymmetric capacitances) can

cause charge transfer to sampling capacitor Csh.

H = switch on

L = switch off

Csh

Uin

ai17909

Csh

Uin

Cext

L --> H switching on

ai17910

AN2834 데이터시트(PDF) 41 Page - STMicroelectronics