Summary

AN3140

12/14

Doc ID 16997 Rev 1

7

Summary

A general purpose timer can be seen as a simple counter with two clocks in input:

READ_Clk (for the slave interface) and CNT_Clk (for incrementing/decrementing the

counter).

The CNT_Clk for the GPT in SPEAr3xx can be selected between a fixed 48 MHz source

and PLL1, which is also the source clock for the rest of the system. The READ_Clk is

derived from PLL1 in normal mode (PCLK) and from the 24 MHz OSCI in slow mode.

Having a fixed clock source different from the system clock has the advantage of eliminating

the need for reconfiguring the GPT registers if the system clock frequency is slowed down.

However, it introduces the possibility of obtaining an unpredictable result when reading the

timer value, due to the non-synchronous operation of the two clocks.