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AN3371 데이터시트(PDF) 30 Page - STMicroelectronics |
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AN3371 데이터시트(HTML) 30 Page - STMicroelectronics |
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30 / 45 page ![]() Overview of the STM32 advanced RTC AN3371 30/45 Doc ID 018624 Rev 5 calendar year field is set to 0x00 (power-on reset value), meaning that the calendar must be initialized. 1.12.3 RTC clock synchronization When the application reads the calendar, it accesses shadow registers that contain a copy of the real calendar time and date clocked by the RTC clock (RTCCLK). The RSF bit is set in the RTC_ISR register each time the calendar time and date shadow registers are updated with the real calendar value. The copy is performed every two RTCCLK cycles, synchronized with the system clock (SYSCLK). After a system reset or after exiting the initialization mode, the application must wait for RSF to be set before reading the calendar shadow registers. When the system is woken up from low power modes (SYSCLK was off), the application must first clear the RSF bit, and then wait until it is set again before reading the calendar registers. This ensures that the value read by the application is the current calendar value, and not the value before entering the Low power mode. By setting the “BYPASHAD” bit to ‘1’ in the RTC_CR register, the calendar values are taken directly from the calendar counters instead of reading the shadow register. In this case, it is not mandatory to wait for the synchronization time, but the calendar registers consistency must be checked by the software. The user must read the required calendar field values. The read operation must then be performed again. The results of the two read sequences are then compared. If the results match, the read result is correct. If they do not match, the fields must be read one more time, and the third read result is valid. Note: After resetting the BYPASHAD bit, the shadow registers may be incorrect until the next synchronization. In this case, the software should clear the “RSF” bit then wait for the synchronization (“RSF” should be set) and finally read the shadow registers. |
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