Low power modes

AN3404

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Doc ID 018847 Rev 3

4.7.1

Entering Halt mode

The MCU enters Halt mode when a HALT instruction is executed. Before executing a HALT

instruction, the application must clear any pending peripheral interrupt by clearing the

interrupt pending bit in the corresponding peripheral configuration register. Otherwise, the

HALT instruction is executed but the MCU wakes up immediately and the program execution

continues.

4.7.2

Exiting Halt mode

Wakeup from Halt mode is triggered by an external interrupt. This wakeup is sourced by a

general purpose I/O port configured as an interrupt input or by an alternate function pin

capable of triggering a peripheral interrupt.

The system clock is then restarted at the last selected clock source before the system

enters Halt mode.

In an interrupt-based application, where most of the processing is done through the interrupt

routines, the main program may be suspended by setting the activation level bit (AL) in the

Global configuration (CFG_GCR) register. Refer to Section 4.9: Activation level control on

page 15.

4.8

Active-halt

In Active-halt mode, the main oscillator, the CPU, and almost all peripherals are stopped.

Only the LSI RC oscillator runs to drive the SWIM and IWDG, if enabled.

4.8.1

Entering Active-halt mode

The user can enter this mode by a HALT instruction, once auto-wakeup (AWU) is enabled or

a ProxSense acquisition is ongoing.

ProxSense acquisition must have started or the AWU must have been correctly configured

and enabled, before executing the HALT instruction.

4.8.2

Exiting Active-halt mode

Wakeup from Active-halt mode is triggered by an external interrupt, a ProxSense interrupt or

an AWU interrupt.

The system clock is then restarted at the last selected clock source before the system

enters Halt mode.

In an interrupt-based application, where most of the processing is done through the interrupt

routines, the main program may be suspended by setting the activation level bit (AL) in the

Global configuration (CFG_GCR) register. Refer to Section 4.9: Activation level control.