Register descriptions

PM0068

24/31

Doc ID 17100 Rev 2

3.6

Flash address register (FLASH_AR)

This register is dedicated to Flash memory bank 1.

Address offset: 0x14

Reset value: 0x0000 0000

Updated by hardware with the currently/last used address. For Page Erase operations, this

should be updated by software to indicate the chosen page.

3.7

Option byte register (FLASH_OBR)

Address offset 0x1C

Reset value: 0x03FF FFFC

Note:

The reset value of this register depends on the value programmed in the option byte and the

OPTERR bit reset value depends on the comparison of the option byte and its complement

during the option byte loading phase.

Bit 0 PG: Programming

Flash programming chosen.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

FAR[31:16]

www

www

w

w

ww

wwww

w

w

15

14

13

12

11

10

9

8

7654

32

1

0

FAR[15:0]

www

www

w

w

ww

wwww

w

w

Bits 31:0 FAR: Flash Address

Chooses the address to program when programming is selected, or a page to erase when

Page Erase is selected.

Note: Write access to this register is blocked when the BSY bit in the FLASH_SR register is

set.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

98765432

10

Reserved

Data1

Data0

Not used

rrrrrrrrrrr

rrrrrrrrrrrrr

rr

Bits 31:25 Reserved, must be kept cleared.

Bits 25:18 Data1

Bits 17:10 Data0