PM0075

Register descriptions

Doc ID 17863 Rev 2

27/31

3.6

Flash address register (FLASH_AR)

Address offset: 0x14

Reset value: 0x0000 0000

Updated by hardware with the currently/last used address. For Page Erase operations, this

should be updated by software to indicate the chosen page.

3.7

Option byte register (FLASH_OBR)

Address offset 0x1C

Reset value: 0x03FF FFFC

Note:

The reset value of this register depends on the value programmed in the option byte and the

OPTERR bit reset value depends on the comparison of the option byte and its complement

during the option byte loading phase.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

FAR[31:16]

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15

14

13

12

11

10

9

8

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32

1

0

FAR[15:0]

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Bits 31:0 FAR: Flash Address

Chooses the address to program when programming is selected, or a page to erase when

Page Erase is selected.

Note: Write access to this register is blocked when the BSY bit in the FLASH_SR register is

set.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

98765432

10

Reserved

Data1

Data0

Not used

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Bits 31:26 Reserved, must be kept cleared.

Bits 25:18 Data1

Bits 17:10 Data0

Bits 9:2 USER: User option bytes

This contains the user option byte loaded by the OBL.

Bits [9:5]: Not used (if these bits are written in the Flash option byte, they will be read in this

register with no effect on the device.)

Bit 4: nRST_STDBY

Bit 3: nRST_STOP

Bit 2: WDG_SW