 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
UPD70741 데이터시트(PDF) 13 Page - NEC |
|
|
|||||||||||||||||||||||||||||
UPD70741 데이터시트(HTML) 13 Page - NEC |
|
|
13 / 112 page  µPD70741 13 2.9 Watchdog Timer (WDT) This block incorporates an 8-bit watchdog timer to detect a program hanging up or system errors. If the watchdog timer overflows, the WDTOUT pin becomes active. 2.10 Clock Generator (CG) Supplies clock pulses at a frequency five times greater than that of the oscillator connected to pins X1 and X2 (when the built-in PLL is being used) or at half the frequency (when the built-in PLL is not being used) of the operating clock pulses for the CPU. Also, instead of connecting an oscillator, external clock pulses can be input. 2.11 Bus Arbitration Unit (BAU) Arbitrates any contention over bus mastership between the bus masters (CPU, DRAMC, DMAC, external bus master). Bus mastership can be switched in each bus cycle and also in the idle state. 2.12 Port Port 0 provides a total of ten input/output port pins. The pins can be used as either port or control pins. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
