Memory organization

PM0212

6/22

Doc ID 022351 Rev 2

2

Memory organization

STM8TL5xxx microcontrollers feature up to 16 Kbytes of Flash program memory including

up to 2 Kbytes of data EEPROM.

A memory accelerator takes advantage of the parallel 4-byte storage, which corresponds to

a word. The Flash program memory and data EEPROM can be erased and programmed at

byte level, word level or block level. In word programming mode, 4 bytes are

programmed/erased during the same cycle, while in block programming mode, a whole

block is programmed/erase during the same cycle.

2.1

Memory features

The STM8TL5xxx memory features are as follows:

●

Up to 16 Kbytes of Flash program memory including up to 2 Kbytes of data EEPROM.

The whole memory array is divided into 256 pages of one block (64 bytes) each.

The Flash program memory is divided into 3 areas:

–

The user boot code area (UBC)

–

A configurable data EEPROM area (DATA)

–

The main program area

The DATA and main program areas can be write protected independently by using the

memory access security mechanism (MASS).

The size of UBC, and DATA areas can be configured through option bytes.

●

One block (64 bytes) of option bytes of which 5 bytes are already used to configure

device hardware features. The option bytes can be programmed only in ICP/SWIM

mode.

Refer to Table 1: STM8TL5xxx memory partitions for a detailed description of STM8TL5xxx

memory partitioning.