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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PM0214 데이터시트(PDF) 216 Page - STMicroelectronics |
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PM0214 데이터시트(HTML) 216 Page - STMicroelectronics |
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216 / 245 page  Core peripherals PM0214 216/245 DocID022708 Rev 4 Bit 3 UNALIGN_ TRP Enables unaligned access traps: 0: Do not trap unaligned halfword and word accesses 1: Trap unaligned halfword and word accesses. If this bit is set to 1, an unaligned access generates a usage fault. Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1. Bit 2 Reserved, must be kept cleared Bit 1 USERSETMPEND Enables unprivileged software access to the STIR, see Software trigger interrupt register (NVIC_STIR) on page 201: 0: Disable 1: Enable. Bit 0 NONBASETHRDENA Configures how the processor enters Thread mode. 0: Processor can enter Thread mode only when no exception is active. 1: Processor can enter Thread mode from any level under the control of an EXC_RETURN value, see Exception return on page 43. |
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