PM0214 datasheet(225/245 Pages) STMICROELECTRONICS

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PM0214

Core peripherals

244

4.4.14

Hard fault status register (HFSR)

Address offset: 0x2C

Reset value: 0x0000 0000

Required privilege: Privileged

The HFSR gives information about events that activate the hard fault handler. This register

is read, write to clear. This means that bits in the register read normally, but writing 1 to any

bit clears that bit to 0.

3029

DEBU

G_VT

FORC

Reserved

rc_w1

Reserved

VECT

TBL

Res.

rc_w1

Bit 31

DEBUG_VT: Reserved for Debug use. When writing to the register you must write 0 to this bit,

otherwise behavior is unpredictable.

Bit 30

FORCED: Forced hard fault. Indicates a forced hard fault, generated by escalation of a fault

with configurable priority that cannot be handles, either because of priority or because it is

disabled.

When this bit is set to 1, the hard fault handler must read the other fault status registers to find

the cause of the fault.

0: No forced hard fault

1: Forced hard fault.

Bits 29:2

Reserved, must be kept cleared

Bit 1

VECTTBL: Vector table hard fault. Indicates a bus fault on a vector table read during

exception processing. This error is always handled by the hard fault handler.

When this bit is set to 1, the PC value stacked for the exception return points to the instruction

that was preempted by the exception.

0: No bus fault on vector table read

1: Bus fault on vector table read.

Bit 0

Reserved, must be kept cleared

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