PM0214 datasheet(241/245 Pages) STMICROELECTRONICS

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DocID022708 Rev 4

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PM0214

Core peripherals

244

4.6.5

Floating-point default status control register (FPDSCR)

Address offset: 0x0C

Reset value: 0x0000000

Required privilege: Privileged

The FPDSCR register holds the default values for the floating-point status control data.

4.6.6

Enabling the FPU

The FPU is disabled from reset. You must enable it before you can use any floating-point

instructions.

The example shows an example code sequence for enabling the FPU in both privileged and

user modes. The processor must be in privileged mode to read from and write to the

CPACR.

Example

; CPACR is located at address 0xE000ED88

LDR.W

R0, =0xE000ED88

; Read CPACR

LDR

R1, [R0]

; Set bits 20-23 to enable CP10 and CP11 coprocessors

ORR

R1, R1, #(0xF << 20)

; Write back the modified value to the CPACR

STR

R1, [R0]; wait for store to complete

DSB

;reset pipeline now the FPU is enabled

ISB

4.6.7

Enabling and clearing FPU exception interrupts

The FPU exception flags (IDC, UFC, OFC, DZC and additionally, in STM32F3xxx devices,

the IXC flag) are ORed and connected to the interrupt controller.

3029

Reserved

AHP

RMode

Reserved

Bits 31:27

Reserved, must be kept cleared.

Bit 26

AHP: Default value for FPSCR.AHP

Bit 25

DN: Default value for FPSCR.DN

Bit 24

FZ: Default value for FPSCR.FZ

Bits 23:22

RMode: Default value for FPSCR.RMode

Bits 21:0

Reserved, must be kept cleared.

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