6

General-purpose timers

In addition to the flash memory interface the timer IP is the same as the one used in the STM32Fxx microcontroller's families, so

almost of the bits and registers are already aligned with the standard naming except the registers that are used to manage the

timer interrupts (INT_TIMxCFG, INT_TIMxFLAG and INT_TIMxMISS registers).

6.1

STM32W108xx Timers Overview

0

Table 15.

TIM bits and registers overview

Offset

(TIM1/

TIM2)

Register

STM32W108xx GPTimer bits/registers naming overview

0xE000

0xF000

TIMx_

CR1

Reserved

TIM_

ARBE

TIM_

CMS

TIM_

DIR

TIM_

OPM

TIM_

URS

TIM_

UDIS

TIM_

CEN

TIMx_

CR1

Reserved

ARPE

CMS

DIR

OPM

URS

UDIS

CEN

0xE004

0xF004

TIMx_

CR2

Reserved

TIM_

TI1S

TIM_MMS

Reserved

TIMx_

CR2

Reserved

TI1S

MMS

Reserved

0xE008

0xF008

TIMx_

SMCR

Res

TIM_

ETP

TIM_

ECE

TIM_ETPS

TIM_ETF

TIM_

MSM

TIM_TS

Res.

TIM_SMS

TIMx_

SMCR

Res ETP

ECE

ETPS

ETF

MSM

TS

Res.

SMS

0xE014

0xF014

TIMx_

EGR

Reserved

TIM_TG

Res

TIM_

CC4G

TIM_

CC3G

TIM_

CC2G

TIM_

CC1G

TIM_

UG

TIMx_

EGR

Reserved

TG

Res

CC4G

CC3G

CC2G

CC1G

UG