Overview of 16-bit SDADC

AN4207

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Doc ID 023945 Rev 1

2.1.6

Low power modes

The 16-bit SDADC combines both high resolution and low power consumption making it

suitable for battery-powered products. If the SDADC is left powered-up continuously, it

consumes 1.2 mA maximum (typically 800 µA). The SDADC has three main modes for

reducing power consumption:

1.

Slow mode: In this mode, the SDADC consumes 600 µA maximum but the sampling

rate is limited to 12.5 Ksps maximum

2.

Standby mode: In this mode, the SDADC consumes a maximum of about 200 µA but a

stabilization time of 300 SDADC clock cycles (50 µs @ 6 MHz) is required each time it

exits from Standby mode.

3.

Power down mode: In this mode, the SDADC consumes a maximum of about 2.5 µA

but a stabilization time of 600 SDADC clock cycles (100 µs @ 6 MHz) is required each

time it exits from Standby mode.