Debug management

AN4661

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DocID027559 Rev 1

5.3.1

SWJ debug port pins

Five pins are used as outputs from the STM32F746xx/STM32F756xx for the SWJ-DP as

alternate functions of general-purpose I/Os. These pins are available on all packages.

5.3.2

Flexible SWJ-DP pin assignment

After RESET (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned

as dedicated pins immediately usable by the debugger host (note that the trace outputs are

not assigned except if explicitly programmed by the debugger host).

However, the STM32F746xx/STM32F756xx devices offer the possibility of disabling some

or all of the SWJ-DP ports and so, of releasing the associated pins for general-purpose IO

(GPIO) usage.

Table 6 shows the different possibilities to release some pins.

For more details on how to disable SWJ-DP port pins, please refer to RM0385 I/O pin

alternate function multiplexer and mapping section.

Table 5. SWJ debug port pins

SWJ-DP pin name

JTAG debug port

SW debug port

Pin

assignment

Type

Description

Type

Debug assignment

JTMS/SWDIO

I

JTAG test mode

Selection

IO

Serial wire data

input/output

PA13

JTCK/SWCLK

I

JTAG test clock

I

Serial wire clock

PA14

JTDI

I

JTAG test data input

-

-

PA15

JTDO/TRACESWO

O

JTAG test data

output

-

TRACESWO if async

trace is enabled

PB3

NJTRST

I

JTAG test nReset

-

-

PB4

Table 6. Flexible SWJ-DP assignment

Available debug ports

SWJ IO pin assigned

PA13 /

JTMS /

SWDIO

PA14 /

JTCK /

SWCL

K

PA15 /

JTDI

PB3 /

JTDO

PB4 /

NJTRST

Full SWJ (JTAG-DP + SW-DP) - reset state

X

X

X

X

X

Full SWJ (JTAG-DP + SW-DP) but without

NJTRST

XXX

X

-

JTAG-DP disabled and SW-DP enabled

X

X

-

JTAG-DP disabled and SW-DP disabled

Released