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UPD750004A 데이터시트(PDF) 3 Page - NEC

부품명 UPD750004A
상세설명  4 BIT SINGLE-CHIP MICROCONTROLLER
PDF  84 Pages
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제조업체  NEC [NEC]
홈페이지  http://www.nec.com/
Logo NEC - NEC

UPD750004A 데이터시트(HTML) 3 Page - NEC

  UPD750004A Datasheet HTML 1Page - NEC UPD750004A Datasheet HTML 2Page - NEC UPD750004A Datasheet HTML 3Page - NEC UPD750004A Datasheet HTML 4Page - NEC UPD750004A Datasheet HTML 5Page - NEC UPD750004A Datasheet HTML 6Page - NEC UPD750004A Datasheet HTML 7Page - NEC UPD750004A Datasheet HTML 8Page - NEC UPD750004A Datasheet HTML 9Page - NEC Next Button
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3
µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)
ROM
RAM
FUNCTIONS
CMOS input
CMOS I/O
N-ch open
drain I/O
Total
8
18
8
34
Can incorporate 7 pull-up resistors that are specified with the software.
Can directly drive the LED.
Can incorporate 18 pull-up resistors that are specified with the software.
Can directly drive the LED.
Can withstand 13 V.
Can incorporate pull-up resistors that are specified with the mask option.
Serial interface
Clock output (PCL)
Buzzer output (BUZ)
Vectored interrupt
Test input
System clock oscillator
Standby
Operating ambient
temperature range
Supply voltage
Package
Item
Command execution
time
Internal memory
General-purpose
register
I/O port
Timer
Bit sequential buffer (BSB)
4 channels
• 8-bit timer/event counter: 1 channel
• 8-bit timer counter: 1 channel
• Basic interval timer/watchdog timer: 1 channel
• lock timer: 1 channel
• Three-wire serial I/O mode ... switchable between the start LSB and the start MSB
• Two-wire serial I/O mode
• SBI mode
16 bits
•
Φ, 524 kHz, 262 kHz, 65.5 kHz (when the main system clock operates at 4.19 MHz)
•
Φ, 750 kHz, 375 kHz, 93.8 kHz (when the main system clock operates at 6.0 MHz)
• 2 kHz, 4 kHz, 32 kHz (when the main system clock operates at 4.19 MHz or when the
subsystem clock operates at 32.768 kHz)
• 2.93 kHz, 5.86 kHz, 46.9 kHz (when the main system clock operates at 6.0 MHz)
External :
3
Internal :
4
External :
1
Internal :
1
• Ceramic or crystal oscillator for main system clock
• Crystal oscillator for subsystem clock
STOP/HALT mode
TA = -40 to +85
°C
VDD = 2.2 to 5.5 V
42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)
44-pin plastic QFP (10
× 10 mm, 0.8 mm pitch)
Function
• 0.95, 1.91, 3.81, 15.3
µs (when the main system clock operates at 4.19 MHz)
• 0.67, 1.33, 2.67, 10.7
µs (when the main system clock operates at 6.0 MHz)
• 122
µs (when the subsystem clock operates at 32.768 kHz)
4096
× 8 bits (
µPD750004)
6144
× 8 bits (
µPD750006)
8192
× 8 bits (
µPD750008)
512
× 4 bits
• When operating in 4 bits: 8
× 4 banks
• When operating in 8 bits: 4
× 4 banks



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