LT1204CSW datasheet(12/20 Pages) LINER

12 / 20 page

LT1204

APPLICATI

I FOR ATIO

When the decoder turns off the tee switch (Q2 on) the

emitter base junctions of Q1 and Q3 become reverse-

biased while Q2 emitter absorbs current from I1. Not only

do the reverse-biased emitter base junctions provide good

isolation, but any signal at VIN0 coupling to Q1 emitter is

further attenuated by the shunt impedance of Q2 emitter.

Current from I2 is routed to any on switch.

Crosstalk performance is a strong function of the IC

package, the PC board layout as well as the IC design. The

die layout utilizes grounds between each input to isolate

adjacent channels, while the output and feedback pins are

on opposite sides of the die from the input. The layout of

a PC board that is capable of providing – 90dB all hostile

crosstalk at 10MHz is not trivial. That level corresponds to

a 30

µV output below a 1V input at 10MHz. A demonstra-

tion board has been fabricated to show the component and

ground placement required to attain these crosstalk num-

bers. A graph of all hostile crosstalk for both the PDIP and

SO packages is shown. It has been found empirically from

these PC boards that capacitive coupling across the pack-

age of greater than 3fF (0.003pF) will diminish the rejec-

tion, and it is recommended that this proven layout be

copied into designs. The key to the success of the SO PC

board #028 is the use of a ground plane guard around Pin

13, the feedback pin.

PDIP PC Board #029, Component Side

1204 AI09

GND

V–

V+

(408) 432-1900

LT1204 VIDEO MUX

DEMONSTRATION BOARD

VIN0

VIN1

VIN2

VIN3

VOUT

ENABLE

S/D

REF

FREQUENCY (MHz)

–120

–100

–80

–60

–40

100

1204 AI07

–20

VS = ±15V

VIN0 = GND

VIN1,2,3 = 0dBm

RL = 100Ω

PDIP

DEMO PCB #029

DEMO PCB #028

All Hostile Crosstalk

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