LT1425CS datasheet(16/20 Pages) LINER

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LT1425

APPLICATIONS INFORMATION

Average supply current (including driver current) is:

ISW

)

IIN = 7mA + DC

where,

ISW = Switch current

DC = On switch duty cycle

Switch power dissipation is given by:

PSW = (ISW)2(RSW)(DC)

RSW = Output switch ON resistance

Total power dissipation of the die is the sum of supply

current times supply voltage plus switch power:

PD(TOTAL) = (IIN • VIN) + PSW

FREQUENCY COMPENSATION

Loop frequency compensation is performed by connect-

ing a capacitor from the output of the error amplifier (VC

pin) to ground. An additional series resistor, often

required in traditional current mode switcher controllers

is usually not required, and can even prove detrimental.

The phase margin improvement traditionally offered by

this extra resistor will usually be already accomplished by

the nonzero secondary circuit impedance, which adds a

“zero” to the loop response.

In further contrast to traditional current mode switchers,

VC pin ripple is generally not an issue with the LT1425. The

dynamic nature of the clamped feedback amplifier forms

an effective track/hold type response, whereby the VC

voltage changes during the flyback pulse, but is then

“held” during the subsequent “switch ON” portion of the

next cycle. This action naturally holds the VC voltage stable

during the current comparator sense action (current mode

switching).

PCB LAYOUT CONSIDERATIONS

For maximum efficiency, switch rise and fall times are

made as short as practical. To prevent radiation and high

frequency resonance problems, proper layout of the com-

ponents connected to the IC is essential, especially the

power paths (primary

and secondary). B field (magnetic)

radiation is minimized by keeping output diode, switch pin

and output bypass capacitor leads as short as possible. E

field radiation is kept low by minimizing the length and

area of all traces connected to the switch pin. A ground

plane should always be used under the switcher circuitry

to prevent interplane coupling.

The high speed switching current paths are shown sche-

matically in Figure 2. Minimum lead length in these paths

are essential to ensure clean switching and minimal EMI.

The path containing the input capacitor, transformer pri-

mary, output switch, the path containing the transformer

secondary, output diode and output capacitor are the only

ones containing nanosecond rise and fall times. Keep

these paths as short as possible.

HIGH

FREQUENCY

CIRCULATING

PATH

•

VOUT

VIN

HIGH

FREQUENCY

CIRCULATING

PATH

ISOLATED

LOAD

1425 F02

Figure 2

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