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UPD75336 데이터시트(PDF) 21 Page - NEC |
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UPD75336 데이터시트(HTML) 21 Page - NEC |
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21 / 68 page ![]() 21 µPD75336 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit is intended to output clock pulses from the P22/PCL pin and is used for remote control or to supply clock pulses to peripheral LSIs. • Clock output (PCL): Φ, 524 kHz, 262 kHz, 65.5 kHz (at 4.19 MHz operation) Fig. 5-2 Clock Output Circuit Configuration CLOM3 CLOM1CLOM0 0 Φ Internal Bus CLOM P22 Output Latch PORT2.2 Bit 2 of PMGB Bit Specified In Port 2 Input/Output Mode Output Buffer PCL/P22 fX/2 3 fX/2 4 fX/2 6 Selector From Clock Generator 4 Remarks The clock circuit is so configured that short-width pulses are not generated when clock output enable/disable is switched. |
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