8

LTC1144

S

APPLICATI

TYPICAL

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7487

© LINEAR TECHNOLOGY CORPORATION 1994

LT/GP 0494 10K • PRINTED IN USA

Regulated –5V Output Voltage

Figure 12 shows a regulated –5V output with a 9V input.

Paralleling for Lower Output Resistance

Additional flexibility of the LTC1144 is shown in Figure 13.

Two LTC1144s are connected in parallel to provide a lower

effective output resistance. However, if the output resis-

tance is dominated by 1/(f

× C1), increasing the capacitor

size (C1) or increasing the frequency will be of more

benefit than the paralleling circuit shown.

Figure 12. A Regulated – 5V Supply

1

2

3

4

8

7

6

5

+

1

µF

100

µF

–5V

9V

36k

300k

1144 F12

LTC1144

2N2369

Figure 13. Paralleling for Lower Output Resistance

C1

10

µF

C2

20

µF

1144 F13

1

2

3

4

8

7

6

5

LTC1144

+

C1

10

µF

1/4 CD4077*

* THE EXCLUSIVE NOR GATE

SYNCHRONIZES BOTH LTC1144s

TO MINIMIZE RIPPLE

1

2

3

4

8

7

6

5

LTC1144

+

0.009 – 0.015

(0.229 – 0.381)

0.300 – 0.320

(7.620 – 8.128)

0.325

+0.025

–0.015

+0.635

–0.381

8.255

()

0.045 ± 0.015

(1.143 ± 0.381)

0.100 ± 0.010

(2.540 ± 0.254)

0.065

(1.651)

TYP

0.045 – 0.065

(1.143 – 1.651)

0.130 ± 0.005

(3.302 ± 0.127)

0.020

(0.508)

MIN

0.018 ± 0.003

(0.457 ± 0.076)

0.125

(3.175)

MIN

12

3

4

87

6

5

0.250 ± 0.010

(6.350 ± 0.254)

0.400

(10.160)

MAX

0.016 – 0.050

0.406 – 1.270

0.010 – 0.020

(0.254 – 0.508)

× 45°

0°– 8° TYP

0.008 – 0.010

(0.203 – 0.254)

0.053 – 0.069

(1.346 – 1.752)

0.014 – 0.019

(0.355 – 0.483)

0.004 – 0.010

(0.101 – 0.254)

0.050

(1.270)

BSC

1

2

3

4

0.150 – 0.157

(3.810 – 3.988)

8

7

6

5

0.189 – 0.197

(4.801 – 5.004)

0.228 – 0.244

(5.791 – 6.197)

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).

S8 Package

8-Lead Plastic SOIC

N8 Package

8-Lead Plastic DIP