14

LTC1096/LTC1096L

LTC1098/LTC1098L

Data Transfer

The CLK synchronizes the data transfer with each bit being

transmitted on the falling CLK edge and captured on the

rising CLK edge in both transmitting and receiving sys-

tems. The LTC1098(L) first receives input data and then

transmits back the A/D conversion result (half duplex).

tied together allowing transmission over just three wires:

Data transfer is initiated by a falling chip select (CS) signal.

After CS falls the LTC1098(L) looks for a start bit. After the

start bit is received, the 3-bit input word is shifted into the

conversion. After one null bit, the result of the conversion

S

APPLICATI

I FOR ATIO

CLK

CS

POWER

DOWN

SGL/

DIFF

MSBF

B0*

B1

B2

B3

B4

B5

B6

B7

NULL

BIT

Hi-Z

HI-Z

START

ODD/

SIGN

DON'T CARE

MSB-FIRST DATA (MSBF = 0)

MSB-FIRST DATA (MSBF = 1)

LTC1096/98 F02

CLK

CS

POWER

DOWN

SGL/

DIFF

MSBF

B0

B1

B2

B3

B4

B5

B6

B7

NULL

BIT

Hi-Z

HI-Z

START

ODD/

SIGN

DON'T CARE

B7*

B6

B5

B4

B3

B2

B1

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.

(MSB)

(MSB)

CS

SHIFT MUX

ADDRESS IN

1 NULL BIT

SHIFT A/D CONVERSION

RESULT OUT

LTC1096/98 • AI01

CS should be brought high. This resets the LTC1098(L) in

preparation for the next data exchange.

The LTC1096(L) does not require a configuration input

as shown in the LTC1096(L) operating sequence. After CS