UPD75P0076 datasheet(4/62 Pages) NEC

4 / 62 page

µPD75P0076

1. PIN CONFIGURATION (Top View)

•

42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

µPD75P0076CU

•

42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)

µPD75P0076GT

Pin Identification

AN0 to AN7

: Analog Input 0 to 7

P110 to P113 : Port 11

AVREF

: Analog Reference

PCL

: Programmable Clock

AVSS

: Analog Ground

PTO0, PTO1 : Programmable Timer Output 0, 1

BUZ

: Buzzer Clock

RESET

: Reset Input

D0 to D7

: Data Bus 0 to 7

SB0, SB1

: Serial Data Bus 0, 1

INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4

SCK

: Serial Clock

INT2

: External Test Input 2

: Serial Input

KR0 to KR3

: Key Return

: Serial Output

MD0 to MD3

: Mode Selection 0 to 3

TI0, TI1

: Timer Input 0, 1

P00 to P03

: Port 0

VDD

: Positive Power Supply

P10 to P13

: Port 1

VPP

: Programmable Power Supply

P20 to P23

: Port 2

VSS

: Ground

P30 to P33

: Port 3

X1, X2

: Main System Clock Oscillation 1, 2

P40 to P43

: Port 4

XT1, XT2

: Subsystem Clock Oscillation 1, 2

P50 to P53

: Port 5

P60 to P63

: Port 6

XT1

XT2

RESET

P33/MD3

P32/MD2

P31/MD1

P30/MD0

AVSS

P63/KR3/AN7

P62/KR2/AN6

P61/KR1/AN5

P60/KR0/AN4

P113/AN3

P112/AN2

P111/AN1

P110/AN0

AVREF

VPP

VDD

VSS

P40/D0

P41/D1

P42/D2

P43/D3

P50/D4

P51/D5

P52/D6

P53/D7

P00/INT4

P01/SCK

P02/SO/SB0

P03/SI/SB1

P10/INT0

P11/INT1

P12/TI1/INT2

P13/TI0

P20/PTO0

P21/PTO1

P22/PCL

P23/BUZ

In normal operation mode, make sure to connect VPP directly to VDD.

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