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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LTC1197CS8 데이터시트(PDF) 3 Page - Linear Technology |
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LTC1197CS8 데이터시트(HTML) 3 Page - Linear Technology |
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3 / 28 page  3 LTC1197/LTC1197L LTC1199/LTC1199L RECO E DED OPERATI G CO DITIO S LTC1197 LTC1199 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS VCC = 5V Operation tsuCS Setup Time CS ↓ Before First CLK↑ 26 26 ns (See Figures 1, 2) thDI Hold Time DIN After CLK↑ LTC1199 26 ns tsuDI Setup Time DIN Stable Before CLK↑ LTC1199 26 ns tWHCLK CLK High Time fCLK = fCLK(MAX) 40% 40% 1/fCLK tWLCLK CLK Low Time fCLK = fCLK(MAX) 40% 40% 1/fCLK tWHCS CS High Time Between Data Transfer Cycles 32 32 ns tWLCS CS Low Time During Data Transfer 13 15 CLK VCC = 5V, VREF = 5V, fCLK = fCLK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted. CONVERTER AND MULTIPLEXER CHARACTERISTICS – 0.05V to VCC + 0.05V LTC1197 LTC1199 PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Offset Error q ±2 ±2 LSB Linearity Error (Note 3) q ±1 ±1 LSB Gain Error q ±4 ±4 LSB No Missing Codes Resolution q 10 10 Bits Analog Input Range V Reference Input Range LTC1197, VCC ≤ 6V 0.2 VCC + 0.05V V LTC1197, VCC > 6V 0.2 6 V Analog Input Leakage Current (Note 4) q ±1 ±1 µA LTC1197L LTC1199L SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS VCC Supply Voltage 2.7 4 2.7 4 V VCC = 2.7V Operation fCLK Clock Frequency q 0.01 3.5 0.01 3.5 MHz tCYC Total Cycle Time 14 16 CLK tSMPL Analog Input Sampling Time 1.5 1.5 CLK thCS Hold Time CS Low After Last CLK ↑ 40 40 ns tsuCS Setup Time CS ↓ Before First CLK↑ 78 78 ns (See Figures 1, 2) thDI Hold Time DIN After CLK↑ LTC1199L 78 ns tsuDI Setup Time DIN Stable Before CLK↑ LTC1199L 78 ns tWHCLK CLK High Time fCLK = fCLK(MAX) 40% 40% 1/fCLK tWLCLK CLK Low Time fCLK = fCLK(MAX) 40% 40% 1/fCLK tWHCS CS High Time Between Data Transfer Cycles 96 96 ns tWLCS CS Low Time During Data Transfer 13 15 CLK |
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