6

LTC1291

I

DAGRA

BLOCK

TEST CIRCUITS

On and Off Channel Leakage Current

5V

A

A

POLARITY

OFF CHANNEL

ON CHANNEL

1291 TC01

3k

100pF

TEST POINT

1291 TC05

WAVEFORM 1

(SEE NOTE 1)

2.0V

90%

10%

WAVEFORM 2

(SEE NOTE 2)

CS

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.

NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.

1291 TC06

INPUT

SHIFT

REGISTER

COMP

SAMPLE

AND

HOLD

12-BIT

CAPACITIVE

DAC

OUTPUT

SHIFT

REGISTER

12-BIT

SAR

CONTROL

AND

TIMING

8

ANALOG

INPUT MUX

2

3

GND

4

CH1

CH0

6

1

CLK

7

CS

1291 BD

5

1.4V

3k

100pF

TEST POINT

1291 TC02