LTC1435AI datasheet(15/20 Pages) LINER

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LTC1435A

APPLICATIONS INFORMATION

conduct during double battery operation, but must still

clamp the input voltage below breakdown of the converter.

Although the LTC1435A has a maximum input voltage of

36V, most applications will be limited to 30V by the

MOSFET BVDSS.

Design Example

As a design example, assume VIN = 12V(nominal), VIN =

22V(max), VOUT = 1.6V, IMAX = 3A and f = 250kHz, RSENSE

and COSC can immediately be calculated:

RSENSE = 100mV/3A = 0.033Ω

COSC = 1.37(104)/250 – 11 = 43pF

Referring to Figure 3, a 4.7

µH inductor falls within the rec-

ommended range. To check the actual value of the ripple

current the following equation is used:

∆I

OUT

= ()( )









1–

The highest value of the ripple current occurs at the maxi-

mum input voltage:

∆I

kHz

L =

()









250

4 7

–

The lowest duty cycle also occurs at maximum input volt-

age. The on-time during this condition should be checked

to make sure it doesn’t violate the LTC1435A’s minimum

on-time and cause cycle skipping to occur. The required on-

time at VIN(MAX) is:

kHz

ON MIN

OUT

IN MAX

()

= ()( )

= ()(

)

250

291

The

∆ILwaspreviouslycalculatedtobe1.3A,whichis43%

of IMAX. From Figure 7, the LTC1435A minimum on-time

at 43% ripple is about 235ns. Therefore, the minimum on-

time is sufficient and no cycle skipping will occur.

The power dissipation on the topside MOSFET can be easily

estimated. Choosing a Siliconix Si4412DY results in:

RDS(ON) = 0.042Ω, CRSS = 100pF. At maximum input volt-

age with T(estimated) = 50

°C:

kHz

MAIN =

() +() °− °

()

[]()

() ( )( )(

0 005 50

0 042

2 5 22

100

250

185

Ω

The most stringent requirement for the synchronous

N-channel MOSFET occurs when VOUT = 0 (i.e. short cir-

cuit). In this case the worst-case dissipation rises to:

SYNC

SC AVG

DS ON

() +

()

( )

With the 0.033

Ω sense resistor ISC(AVG) = 4A will result,

increasing the Si4412DY dissipation to 950mW at a die tem-

perature of 105

°C.

CIN is chosen for an RMS current rating of at least 1.5A at

temperature. COUT is chosen with an ESR of 0.03Ω for low

output ripple. The output ripple in continuous mode will be

highest at the maximum input voltage. The output voltage

ripple due to ESR is approximately:

VORIPPLE = RESR(∆IL) = 0.03Ω(1.3A) = 39mVP-P

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC1435A. These items are also illustrated graphically in

the layout diagram of Figure 10. Check the following in your

layout:

1. Are the signal and power grounds segregated? The

LTC1435A signal ground pin must return to the (–) plate

of COUT. The power ground connects to the source of the

bottom N-channel MOSFET, anode of the Schottky di-

ode, and (–) plate of CIN, which should have as short lead

lengths as possible.

2. Does the VOSENSE pin connect directly to the feedback

resistors? The resistive divider R1, R2 must be con-

nected between the (+) plate of COUT and signal ground.

The 100pF capacitor should be as close as possible to

the LTC1435A.

3. Are the SENSE– and SENSE+ leads routed together with

minimum PC trace spacing? The filter capacitor between

SENSE+ and SENSE – should be as close as possible to

the LTC1435A.

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