LTC1555IGN datasheet(9/12 Pages) LINER

9 / 12 page

LTC1555/LTC1556

I/O pin on the SIM side. The second method is to use the

DDRV pin to send data to the SIM and use the DATA pin to

receive data from the SIM. When the DDRV pin is not used,

it should either be left floating or tied to DVCC.

Level Translation with DVCC > VCC

It is assumed that most applications for these parts will

use controller supply voltages (DVCC) less than or equal

to VCC. In cases where DVCC is greater than VCC by more

than 0.6V or so, the parts’ operation will be affected in the

following ways: 1) A small DC current (up to 100

µA) will

flow from DVCC to VCC through the DATA pull-up resistor,

N-channel pass device and the I/O pull-up resistor

(except when the part is in shutdown at which time DVCC

is disconnected from VCC by turning off the pass device).

If the VCC load current is less than the DVCC current, the

VCC output may be pulled out of regulation until sufficient

load current pulls VCC back into regulation. 2) When the

SIM is sending data back to the controller, a logic high on

the I/O pin will result in the DATA pin being pulled up to

[VCC + 1/3(DVCC – VCC)], not all the way up to DVCC. For

example, if DVCC is 5V and VCC is 3V, the DATA pin will

only swing from

≈0.1V to 3.67V when receiving data

from the SIM side.

Optional LDO Output

The LTC1556 also contains an internal LDO regulator for

providing a low noise boosted supply voltage for low power

external circuitry (e.g., frequency synthesizers, etc.) Tying

the FB pin to the LDO pin provides a regulated 4.3V at the

LDO output (see Figure 4). A 3.3

µF (minimum) capacitor is

APPLICATIONS INFORMATION

required to ensure output stability. A 10

µF low ESR capaci-

tor is recommended, however, to minimize LDO output

noise. The LDO output may also be used as an auxiliary

switch to VCC. If the FB pin is left floating or is tied to GND,

the LDO pin will be internally connected to the VCC output

through the P-channel pass device. The LDO may be dis-

abled at any time by switching the EN pin from DVCC toGND.

The 4.3V LDO output is usable only when VCC is 5V (or

greater). It is not available when VCC = 3V.

Figure 4. Auxiliary LDO Connections (LTC1556 Only)

VREF

61k

VCC = 5V

µA

LDO

OFF

µF

TANT

4.3V

1555/56 F04

ILDO

0mA to

10mA

FB 153k

10kV ESD Protection

All pins that connect to the SIM (CLK, RST, I/O, VCC, GND)

withstand over 10kV of human body model (100pF/1.5k

Ω)

ESD. In order to ensure proper ESD protection, careful

board layout is required. The GND pins should be tied

directly to a GND plane. The VCC capacitor should be

located very close to the VCC pin and tied immediately to

the GND plane.

LTC1555IGN 데이터시트(PDF) 9 Page - Linear Technology

LTC1555IGN 데이터시트(HTML) 9 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

데이터시트 다운로드

링크 URL