7

LTC1665/LTC1660

BLOCK DIAGRA

GND (Pin 1): System Ground.

Voltage Outputs. The output range is

0

255

256

1665

0

1023

1024

1660

to

V

for the LTC

to

V

for the LTC

REF

REF

















REF (Pin 6): Reference Voltage Input. 0V

CS/LD (Pin 7): Serial Interface Chip Select/Load Input.

into the register. When CS/LD is pulled high, SCK is

disabled and data is loaded from the shift register into the

specified DAC register(s), updating the analog output(s).

CMOS and TTL compatible.

SCK (Pin 8): Serial Interface Clock Input. CMOS and TTL

compatible.

is shifted into the 16-bit register on the rising edge of SCK.

CMOS and TTL compatible.

chain operaton. CMOS and TTL compatible.

CLR (Pin 11): Asynchronous Clear Input. All internal shift

and DAC registers are cleared to zero at the falling edge of

the CLR signal, forcing the analog outputs to zero scale.

CMOS and TTL compatible.

2

15

1

GND

REF

CS/LD

SCK

CLR

1665/60 BD

16

DAC A

DAC H

3

14

DAC B

DAC G

4

13

DAC C

DAC F

5

7

6

8

10

11

9

12

DAC D

DAC E

ADDRESS

DECODER

CONTROL

LOGIC

SHIFT REGISTER

(LTC1665/LTC1660)